rockchip: clk: rk3128: fix NANDC_PLL_SEL_MASK

The PLL selector field for NANDC is only 2 bits wide.
This fixes an 'int-overflow on shift' warning.

Fixes: 9246d9e ("rockchip: rk3128: add clock driver")
Signed-off-by: Philipp Tomsich <[email protected]>

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3128.h b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h
index cc317dc405eaf2873c7b392f08eb605ea04aa004..3d8317ed91b858701acf6e149e6544ca199db547 100644 (file)
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3128.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h
@@ -136,7 +136,7 @@ enum {
 
        /* CRU_CLK_SEL2_CON */
        NANDC_PLL_SEL_SHIFT     = 14,
-       NANDC_PLL_SEL_MASK      = 7 << NANDC_PLL_SEL_SHIFT,
+       NANDC_PLL_SEL_MASK      = 3 << NANDC_PLL_SEL_SHIFT,
        NANDC_PLL_SEL_CPLL      = 0,
        NANDC_PLL_SEL_GPLL,
        NANDC_CLK_DIV_SHIFT     = 8,